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<p>Jan. 27, 2006 </p>

Semitool expects fiscal second quarter revenue to be in the range of $61-to-$64 million, and second quarter earnings per share of between $0.11 and $0.16.

Simon Yang, chief technology officer for Chartered Semiconductor Manufacturing, said he'd like the group to develop new ways of testing without damaging the dinner-plate-sized 300-mm wafers, which can cost as much as $10,000 today.

Several executives at the Semico event said the fab of the future will tie together design and manufacturing tools.

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What needs to be built is a bidirectional highway between design and manufacturing tools,” said Mike McAweeney, vice president of industry alliances at Cadence Design Systems Inc.

— Mark LaPedus contributed to this report .

SAN JOSE, Calif. &#151 Semitool Inc., a manufacturer of wafer processing equipment for the semiconductor industry, said first quarter revenue increased 13 percent to $55.3 million, versus revenue of $48.8 million in the first fiscal quarter of 2005.

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Net income was $63,000, or less than $0.01 per share, versus net income of $5.0 million, or $0.17 per share, in last year's comparable quarter. The lower-than-expected bottom-line performance resulted primarily from the decline in gross margin.

Larry Murphy, president and chief operating officer at Semitool (Kalispell, Mont.), was upbeat. The first quarter was a very strong period for Semitool,” he said in a statement. In addition to our top-line growth, we recorded $65.5 million in bookings, which represented our strongest quarterly bookings performance in more than five years.”

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The $65.5 million in bookings represented an increase of 56 percent from the $42.0 million reported in the first quarter last year.

Semitool expects fiscal second quarter revenue to be in the range of $61-to-$64 million, and second quarter earnings per share of between $0.11 and $0.16.

At sub-100 nm nodes, there are more sophisticated rules about how vias need to sit within layers of metal that surround them,” Brashears said. With Chip Optimizer, we're able to have a set of constraints that go beyond design rule checking (DRC) to find locations for each of the vias in the metal.”

Chip Optimizer can also move wires around, but it's not a geometrically-driven wire spreading tool, Brashears noted. This is really driven by manufacturing and electrical analysis, so the final location of the interconnect is actually better,” he said.

Chip Optimizer is built on the OpenAccess database, and can work with hierarchical or flat designs. Input includes LEF and DEF layout files, Verilog, timing and power constraints, and recommended manufacturing rules. The tool can run automatically or be guided by the user. The output, said Brashears, is simply the same design with better interconnect.”

Chip Optimizer is available immediately. Cadence has not released pricing information.

Zichron Yaacov, Israel — The bullet points are impressive: Israeli high-tech companies are the third-largest group of foreign firms listed on the Nasdaq. Since 1997, more than 80 foreign venture capitalists and corporate venture funds have poured upward of $1.5 billion into local startups. Industry giants like Intel, Cisco, Siemens, Hewlett-Packard and Texas Instruments have invested more than $7 billion in R&D centers in Israel over the past two years. Those companies and other multinationals shelled out nearly $3 billion to buy Israeli startups in 2005, up from $1.8 billion in 2004.