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<p>Let's look at how a poorly coded application, or one that hogs the processor by spinning” (see code sample below), can quickly drain a battery. In this example, the processor will be active for 100 percent of the thread's time slice. Ideally, threads should do their work and then block on a wait object to allow the operating system to drop back into a low-power state.</p>

Figure 21 shows the interface protocol.

It is difficult to use a value of Cgd for the fall time period of VDS (tvf =t3 ). Therefore if the data sheet value of gate charge is used (Qgd_d ) and divided by the voltage swing seen on the drain connection (VDS_D minus VF_D ) then this effectively gives a value for Cgd based on the datasheet transient.

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Similarly for the turn-off transition, the voltage rise time (tvr =t5 ) is:

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Comparing equations with datasheet values The definition of the turn-on and turn-off times given in the datasheet can be seen in Figure 5 . These definitions can be equated to the equations described above and are shown here:

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On a circuit level, ST uses clock-gating and operand-isolation techniques to turn off inactive parts of Nomadik. To reduce static power dissipation, most of the chip can be powered off and reawakened in under 3 ms. The use of on-chip frequency and power scaling, whereby different parts of the chip run at different clock rates and different operating voltages, save power as well. Voltage scaling has its limitations however—it doesn't scale well with reductions in processing nodes. Smaller process nodes support lower operating voltages, so for future devices at 65nm and 1V, there is not a lot of margin for scaling the voltage lower. Circuit-level tricks” can provide a few tens of percent of power savings.

Nomadik is implemented with a combination of low-Vt (high speed, high leakage) and high-Vt (low speed, low leakage) transistors. ST designed the chip so that low-Vt devices are used only where needed for performance. High-Vt transistors are used elsewhere to minimize leakage for 'off' devices. Back biasing of the chip along with the use of optimized cell libraries also result in lower power.

Packaging is another area in which power can be saved. Nomadik can be packaged with stacked Flash memory, minimizing memory-processor interconnects and further reducing power for the packaged chip.

ASICsSince the ASIC vendor develops a fixed-function chip for one customer, usually targeting a single application, they can do everything necessary at all design levels—system, architectural, circuit, and device—to reduce power. Some popular system- and circuit level techniques for ASIC power reduction include multiple clock sources (running different sections of the chip from different clocks), multiple voltage regions (beyond the usual one voltage for the chip's entire core and one for the I/Os), and operation modes that shut down or run at very low speed sections of a chip not in use. If certain chip domains are powered by power lines that are separate from the main power grid these domains, when not used, can have their power totally cut off, eliminating leakage current for these modules. Optimizing on-chip memory configurations reduces power-hungry off-chip memory accesses, which can be a significant part of the chip's dynamic power consumption.

Physical layout for ASICs targeted for ultra-low-power applications benefits from squeezing chip functions into a minimum area, reducing interconnect wire lengths for both clock and data lines. This has a significant impact on dynamic power consumption, since shorter signal and data paths translate to lower power dissipation. For power-critical applications, ASIC designers may also custom-design individual logic blocks, or even individual transistors, to minimize power commensurate with chip timing specifications.