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<p>As mentioned at the outset of the article, we're considering the implementation of a four-finger RAKE receiver. MRC is just a complex multiplication with a channel coefficient in each finger, followed by addition of the results from the different fingers. These steps can be combined using MAC instructions.</p>

Det gäller också att man verkligen känner till de dielektriska materialens egenskaper eftersom toleranskraven är högre än för standardprocesser. Inte minst är det viktigt att man känner till dielektrikats mekaniska egenskaper så att det inte uppstår några sprickningar i resistormaterialet under produktionsprocessen.

Napper said STMicroelectronics will tape out a DVD chip in February that contains a Pico-designed block.

Synfora plans a first-quarter announcement of its initial product, available both off-the-shelf and through a service in which Synfora will produce designs for customers.

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While Synopsys continues to claim 90 percent of the ASIC synthesis market, a few users are taking a look at alternatives. One is Chris Malachowsky, CTO at graphics developer Nvidia. The Santa Clara, Calif., company has purchased Cadence's Get2Chip RTL Compiler to use alongside Synopsys' Design Compiler, so that its designers can try different optimization engines on their designs.

Our addition of RC [RTL Compiler] into our tool mix is not in any way an indication of how we feel about DC [DesignCompiler], which, in fact, we consider to be one of the premier tools in our flow,” said Malachowsky. We decided to give ourselves the benefit of being able to apply multiple optimization strategies to our designs.”

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While DesignCompiler is rock-solid, battle-proven technology,” Malachowsky said, RTL Compiler is a robust tool that takes a different approach to the optimization problem. We feel RC is also good technology,” he said. He declined, however, to provide any comparative data between the two, or to indicate situations in which one might perform better than the other.

Infrant Technologies, a networking startup in Fremont, Calif., decided to bypass Synopsys entirely and use Magma's Blast Create in conjunction with Blast Fusion. Paul Tien, Infrant's CEO, said that while the Synopsys product historically cannot handle large databases, Magma's tool can synthesize an entire chip in one chunk. Infrant used it to tape out a 3-million-gate, 250-MHz network storage design, he said.

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Because Magma's synthesis is closely tied to its back-end tools, it yields better timing prediction, Tien said. You probably don't need to over-synthesize, which a lot of Synopsys users are used to doing,” he said. But Tien noted that the early version of Blast Create didn't have a design-for-test capability, and that Magma doesn't yet have anything comparable to Synopsys' DesignWare library.

Peter Parsons, president of ASIC and FPGA design house Pinpoint Solutions (Boulder, Colo.), is a happy user of Synplicity's Synplify ASIC product. He said that after trashing” with an FPGA-to-ASIC design conversion using Design Compiler, Pinpoint was able to quickly get results with Synplify ASIC.

Amkor's QFN product family includes the proprietary MicroLeadFrame (MLF) line, while ASAT's QFN product family includes the proprietary Leadless Plastic Chip Carrier (LPCC).

Imagine partitioning a packet forwarding application across two or more programmable network processing elements (NPEs). In order to avoid re-parsing the packet on multiple NPEs, the developer of the packet-forwarding program would like to enable a downstream NPE to easily access relevant packet data derived from an upstream NPE. For example, in a system with an upstream classification NPE connected to a downstream traffic management NPE, the results of the per-packet classification need to be communicated to the traffic management NPE in a standard way.

The Network Processing Forum’s recently adopted Message Layer Implementation Agreement (IA) defines a standard format to communicate such packet-related data between two NPEs across streaming and look-aside interfaces as well as switch fabrics. In the article to follow, we'll take a look at the new Message Layer IA, showing the key elements that are needed to make this IA work. We'll then demonstrate how this mechanism can be used to pass data between two NPEs.

Why Need a Message Layer? In a typical network processing design, NPEs need to exchange messages in order to properly communicate. These messages contain data from, or derived from, the packet being processed or that must be communicated between two NPEs to properly process the packet. This data could be extracted from the packet (such as a destination IP address), or it could be a unique value that represents the information contained in several fields of a packet (such as a flow classification), or it could identify the associated context for interpreting the packet (such as a port or channel identifier).

The Message Layer IA specifies a standard interoperable mechanism for sharing this data between NPEs in-band and with low overhead. This IA augments the existing Network Processing Forum (NPF) physical layer IAs, including Streaming Interface, Look-Aside Interface, and CSIX. Specifically, these physical layer IA's define interfaces for exchanging data, but they do not define the contents of the data—forcing system designers to develop their own proprietary approaches for sharing data. With the Message Layer IA, system designers can now rely on a standard format and definition for the contents of data shared between NPEs from different vendors.