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<p>The formula itself could be improved by adding a constant baseline to the SNR (the traditional water-filling” term). But in reality the jitter estimate is hardly impacted by this mathematical accident, since forcing the Levenberg-Marquardt algorithm to fit the experimental minimum or not just causes differences of a few femtoseconds. In fact, the difference between the maxima and minima of the voltage noise represented in Figure 3 are to be calculated in rms terms, and as such any inaccuracy in the lower part of the plots weighs significantly less than an error in the top of the curve. However, this also causes any high jitter spikes” often observed during this kind of characterization to completely falsify the jitter estimate achieved through the technique, if only zero-crossing and input peak were used.</p>

References

About the Authors Asher Hazanchuk is a senior manager of DSP applications and architectures at Altera. Asher has a master's degree in Computer Science and a bachelor's degree in Electrical Engineering. He can be reached at

LHL10NB393J_Taiyo Yuden_Fixed Inductors

Sheac Yee Lim is a senior applications engineer in the product applications group at Altera. She has a master's degree in Electrical Engineering and can be reached at .

LHL10NB393J_Taiyo Yuden_Fixed Inductors

LHL10NB393J_Taiyo Yuden_Fixed Inductors

This article is an introduction to the application of serial switched PCI in systems designs. Serial Switched PCI inherently provides key benefits of increased flexibility, scalability, and reliability, and eliminates many limitations inherent in bus-based architectures. The article will introduce the architectural freedoms resulting from these benefits, as well as the class of service capabilities available from serial switched PCI technologies. In particular, this article will demonstrate how the application of serial switched PCI expands the capabilities of existing PCI based designs. Several real world applications illustrate the benefits and ease of use of StarFabric, the only shipping serial switched PCI technology.

Typical computing systems operate with a number of interconnects, designed to optimize specific attributes for system sub-sections. Local, proprietary parallel buses connect CPU, chipset, and cache/memory; these buses are very short and designed to maximize speed. A mezzanine bus is commonly used to connect devices within the system chassis. The mezzanine bus has also been a shared parallel connection that connects graphics, storage, and communications modules to the system chipset. It is designed with goals of performance and flexibility in the number and type of attached devices. The building-level LAN (a serial connection designed for moderate distance and performance over low cost cabling) is commonly used outside the system chassis—between systems, clients, and networked storage. It is a serial connection running over low cost cabling, at lower performance levels and moderate distance. Both the mezzanine and LAN are conventionally built to industry standard architectures to take advantage of the number of standards compliant devices.

The payload can contain either a management message or transport data. Specific connections are set aside as management connections and these carry management messages and not anything else. All other channels are transport channels that do not carry management messages.

A payload in a transport connection can contain a MAC service data unit (MSDU), fragments of MSDUs, aggregates of MSDUs, aggregates of fragments of MSDUs, bandwidth requests or retransmission requests according to the MAC rules on bandwidth requesting, fragmentation, packing and ARQ. Figure 4 shows a variety of typical frame formats.

Bandwidth Request PDUs To request changes to the granted characteristics of a connection, a 6-byte bandwidth request header is transmitted in place of the GMH. The header type (HT) bit is set to 1 to indicate that the header is a bandwidth request header and not a GMH. The contents of bandwidth request header is as shown in Figure 5 .