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<p>Current products from NSC-Nanosemiconductor incude quantum dot lasers for telecom applications, as well as high-yield micro-electronics components. Planned future products include high-brightness light-emitting diodes (HB-LEDs) for replacing incandescent lighting, and technology to enable integration of optical and wireless functionality on silicon-based microprocessor chips.</p>

These advanced traffic management mechanisms provide for the fine grained management of individual traffic classes within the system. Class-based queuing improves the fabric's ability to provide more deterministic latency for special traffic classes. For example voice traffic may be prioritized over email traffic as it traverses the fabric backplane.

SAN JOSE, Calif. — The insight that scaling CMOS devices reduces operating voltage and channel dimensions at roughly the same rate wasn't widely understood until a decade after Gordon Moore's 1965 paper on the power of scalability in CMOS process technology, according to the keynote speaker at this year's International Conference on Computer-Aided Design (ICCAD) here.

Mark Horowitz, Stanford University professor, Rambus cofounder and self-described low-level design guy, provided an overview in his keynote address of the sources, discontents and distant future of CMOS scaling.

RNC55H10R0FPRSL_Vishay Dale_Through Hole Resistors

The realization that scaling CMOS devices reduces operating voltage and channel dimensions at about the same rate tends to keep the electric field intensity inside MOS transistors relatively constant.

Since MOS device behavior depends primarily on electric field strength rather than voltage or current, Horowitz observed, MOS transistors ” and the circuits made from them ” have tended to behave about the same way in each new process. This has proven important to the industry, Horowitz said, because it means, in effect, a second chance for both circuit and tool designers. Instead of creating a whole new wheel in each technology generation, designers have been able to preserve experience from each generation of chips and tools, leveraging that knowledge to attack new problems that come with each new process.

This lasted through the 1980s, Horowitz said. But in the 1990s trouble came from another source: While transistors continued to scale well, wires did not. Interconnect metal evolved from broad, flat segments to tall, narrow segments, and the aspect ratio became more and more extreme, finally stopping at about 2:1.

RNC55H10R0FPRSL_Vishay Dale_Through Hole Resistors

But Horowitz said intense work on interconnect design and signal integrity analysis in the 1990s has essentially removed this stasis as an obstacle to scalability.

Now, Horowitz said, we are facing several new challenges to scalability. The first is design cost, and Horowitz was quick to point out that the problem isn't mask cost or wafer cost, but the cost of the design itself.

RNC55H10R0FPRSL_Vishay Dale_Through Hole Resistors

It costs about $20 million today to put together a company to design an ASIC,” he estimated. He blamed much of the cost on validation. Horowitz complained that existing validation techniques still force designers to deal with the entire complexity of the chip. What is needed for scaling, he said, is an approach to validation that hides the complexity of the blocks being assembled while focusing instead on validating the inaction of blocks.

The effort must be proportional to the number of components I'm putting together, not to their total internal complexity,” he said.

LSI Logic said it is considering an initial public offering for the storage systems company in the first half of 2004, depending on market conditions then. Sometime after an IPO, LSI Logic may distribute to its stockholders the remaining shares of the storage systems business in a tax-free transaction or sell or hold any portion of the shares, the company said.

Corrigan noted that the current executive team that made the subsidiary a success will remain in place. Tom Georgens, president of LSI Logic's Storage Systems subsidiary for the past five years, is to serve as chief executive officer of the storage systems company, LSI Logic said.

We have expanded and strengthened our customer relations and strategic partnerships,” Georgens said.

LONDRES – Intel Corp. a racheté Mobilian Corp., fabricant de puces LAN sans fil, pour un montant resté secret. Selon le fabricant de puces, cet accord renforce sa stratégie qui vise à proposer toute une gamme de puces destinées aux appareils de téléphonie et autres.

Mobilian Corp., start-up de 70 employés, est la dernière acquisition en date réalisée par Intel dans le secteur des communications. Plusieurs de ces acquisitions ont concerné le secteur des appareils sans fil.