San Jose, Calif. — The CT2 series of 2.5-Gbit/s SFP MSA transceivers has been unleashed for telecom and datacom applications. This device handles OC-48, OC-12, and OC-3 operation while also delivering the 1310 and 1550-nm wavelengths needed to operate in short, intermediate, and long-reach applications.

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<p>The companies say the test suite, comprised of a hardware (customer premises equipment (CPE) and software component, is intended to provide a 'gold standard,' ensuring standards-compliance, interoperability between DSLAM vendors, and full validation of G.shdsl line performance.</p>

San Jose, Calif. — The CT2 series of 2.5-Gbit/s SFP MSA transceivers has been unleashed for telecom and datacom applications. This device handles OC-48, OC-12, and OC-3 operation while also delivering the 1310 and 1550-nm wavelengths needed to operate in short, intermediate, and long-reach applications.

In general, the solutions to problems with skew are based on analog designs and techniques that carry a costly penalty in terms of both power dissipation and size. New digital design methods have been shown to offer superior performance in size and power over their analog equivalent solutions. This article will address the advantages of digital design techniques in the implementation of these new high-performance interfaces.

As the speed of the data transfer increases, the amount of time that a particular bit remains valid (known as a unit interval” or bit time”) decreases. At gigabit speeds, the amount of skew that exists between any two lanes becomes proportional to the bit time of the data being transferred. Furthermore, the amount of skew that exists between the lanes of the interface is largely unknown. Hence, when data is received at the destination node, the bits are no longer word-aligned” as when they were transmitted, preventing the use of a simple register to receive the data.

M55342K06B11B8RT5_Vishay Dale_Chip Resistor - Surface Mount

To solve that problem, interfaces such as PCI Express, XAUI and the SPI standards make use of serializer/deserializers (serdes) to transfer the data and re-collate” or word align” at the destination. Typically, the serdes are analog-based designs that employ phase-locked loops (PLLs) or delay-locked loops (DLLs).

The challenge now becomes how to implement a large number of PLL/DLL blocks for a multigigabit interface that is in close proximity to high-speed digital circuit blocks. That task manifests itself in multiple ways.

Electrical noise in electronic systems can be classified either as device/component or man-made, the latter of which is generally coupled or conducted into a circuit from external sources. While electrical noise appears in both analog and digital systems, its effects on each are different. For small-signal circuits in analog systems, noise is a major concern because the desired signal and the noise signal are processed identically, which creates the potential for corrupted data. Hence, it is highly preferable to maintain a large signal-to-noise ratio.

M55342K06B11B8RT5_Vishay Dale_Chip Resistor - Surface Mount

In the implementation of an analog circuit such as a PLL or DLL, conducted noise is always an issue. In particular, when placing multiple PLL and DLL blocks in close proximity to digital blocks or to each other, careful attention must be paid to conducted noise between the various blocks. Supply rail noise, often generated by switching logic, I/O circuits or other PLL and DLL blocks, is another form of conducted noise that must be addressed.

Threshold voltages

M55342K06B11B8RT5_Vishay Dale_Chip Resistor - Surface Mount

In digital circuits, electrical noise usually results in timing variation (i.e., jitter or push-out), and the extent is highly dependent on the amount of noise present and the noise margin of the particular technology. In a binary circuit, recognition of a signal as either a logic 0 or logic 1 depends on whether its voltage is above or below a given set of thresholds. The values of those threshold voltages determine the noise margin and the amount of noise that can be tolerated by the system.

In analog systems, a significant percentage of the power is dissipated in the biasing networks, which draw a dc current whether the circuit is active or not. Also, biasing networks have an additional area penalty that increases if a PVT (process, voltage temperature) compensation circuit is required.

Oh, the menus change once in a while, depending on customer feedback.”

And the playroom?”

That changes sometimes, too,” the manager replied, also depending on customer feedback.”

You seem to depend a lot on customer feedback,” Charlie said.

Oh yes,” he was told. In fact, you know how it is when you first get to work in the morning? You have so much to do that you don't know what to tackle first? Well, we know. First thing in the morning, we go through the feedback we get from suggestion boxes that are prominent all over the store. And we pay attention.”