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<p> Why are process engineers so determined to upset the apple cart? The short answer is short-channel effects. Pursuit of Moore’s Law has continually shrunk the channel length of the MOSFET. This contraction improves transistor density and, other factor fixed, switching speed. The problem is that shortening the channel plays havoc with those other factors—about a dozen different havocs, actually, that get lumped under the label of short-channel effect. Most of these we can summarize by a generalization: as the drain gets closer to the source, it gets harder and harder for the gate to pinch off the channel current (figure 1.) The result is sub-threshold leakage current.</p>

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Standing against all these advantages are three relatively non-technical issues. First, fdSoI wafers are more expensive than conventional wafers. But last week wafer vendor Soitec distributed a report from analyst IC Knowledge claiming that because of the significantly simpler processing to provide multiple threshold voltages on fdSoI wafers, the total cost of a processed wafer at 22/20 nm would be no greater for fdSoI than for planar or finFET processes.

Second, there is risk. Soitec is the only source of wafers for fdSoI, and creating the wafers requires executing the company’s oxide-deposition, wafer-splitting, and polishing steps with atomic-level precision. Soitec delivers the wafers with a uniform 12 nm film of silicon over a similarly thin buried oxide layer. Third, there is inertia. Many senior decision-makers won’t consider anything that’s called SoI. Still some companies will press ahead. AMD, through its Globalfoundries connection, IBM, and ST are probably committed to fdSoI at 22nm. In fact Globalfoundries, which in the past has not aggressively marketed SoI to customers not already using the process, may use fdSoI as an ace up the sleeve to counter pressure from Intel and to trump TSMC. Some fabless IC vendors who have used partially-depleted SoI already, such as Broadcom, are likely to listen to this argument. Beyond this core, though, fdSoI may just not get the attention,” one insider worried.

RNC60H5421DSRE8_Vishay Dale_Through Hole Resistors

There is one more announced player in this race. SuVolta recently announced a process in which the start-up uses deposition to create a buried junction under the channel of a conventional bulk planar MOSFET. Reverse-biasing this junction creates a depletion region under the channel that in effect mimics the buried oxide layer of fdSoI, thinning the active region of the channel until the gate can almost fully deplete it.

The SuVolta technology is interesting, but not widely known outside of a few non-disclosure partners of the start-up company. Consequently, there has not been independent verification of the characteristics of the SuVolta mostly-depleted transistor. None the less, this may be an important alternative for smaller fabs—not unlike Fujitsu—that haven’t the funding to enter the finFET race, and don’t want to pay the extra initial cost for fdSoI wafers.

So there are the players. TSMC seems committed to supply a planar 20 nm process, at least to its initial customers. But it may do a quick revision, and offer a finFET option for mobile applications well before it releases a 16 nm process. Intel is clearly committed to its finFET. IBM, and parts of the Globalfoundries and ST capacity at 22 nm will likely be using fdSoI. Fujitsu will probably continue to exploit their joint development with SuVolta. How the other players line up will undoubtedly depend on customer demands and on early process learning from the major players. If 28 nm proved anything, the lesson was that the course of new process technology doesn’t often run smooth.

RNC60H5421DSRE8_Vishay Dale_Through Hole Resistors

In today's smart grids, utility companies are using data collectors to help track consumption, monitor functionality, and analyze operations. The data collector circuitry is typically located between the  electronic meters (e-meters) that measure usage and the grid's upstream network. The device gathers inputs from the e-meters, performs a certain amount of data processing, and then relays or uploads the centralized data to the network.

The design of a data collector varies, depending on several factors, including the type of power line (single or polyphase), and the functional requirements of the utility system (residential or industrial). In general, though, data collectors fall into three familiar categories — entry-level, mid-range, and high-end. In this article, we look at each category and discuss the data processing and system resource requirements to consider when choosing a microcontroller for the design.

RNC60H5421DSRE8_Vishay Dale_Through Hole Resistors

Entry-level data collectors

Entry-level data collectors, as their name implies, meet relatively basic system requirements. They typically support single-phase power lines (the set-up most often used with residential meters), and collect digital data from an Automatic Meter Reader (AMR), or an upgraded smart meter with digital outputs. Inputs are usually stored in local Flash memory (either embedded or external), and the centralized data is transmitted upstream at a predetermined time via a selected communication interface.

Research director Michael Liard notes, The fastest-growing application between now and 2016 will be item-level tracking in supply-chain management, which ABI Research estimates will exceed a 37% growth rate.”

This growth is being driven by high-volume demand for passive UHF systems to support…

The fastest-growing verticals over our five-year forecast period (in descending order) will be retail CPG, retail in-store, healthcare and life sciences, diverse non-CPG manufacturing, and commercial services,” says Liard.

More specifically, primary RFID applications can be broken down into traditional” and modernizing” types. In the former group are access control, animal ID, automotive immobilization, AVI and e-ID documents. The modernizing category includes asset management, baggage handling, cargo tracking and security, point-of-sale contactless payment, real-time location, supply chain management, and ticketing. The 2011-2016 CAGR for aggregated modernizing applications is expected to be double that of the traditional applications cluster.

Visit ABI Research at http://www.abiresearch.com .